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SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states., , , and . ITC, page 1-8. IEEE Computer Society, (2013)Deeply hardware-entangled reconfigurable logic and interconnect., , , and . ReConFig, page 1-8. IEEE, (2015)Secure hardware-entangled field programmable gate arrays., , , , and . J. Parallel Distrib. Comput., (2019)A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes., , , , and . ICCD, page 523-528. IEEE Computer Society, (2009)Statistical Learning in Chip (SLIC)., , , , , , , and . ICCAD, page 664-669. IEEE, (2015)An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS., , , and . ESSCIRC, page 65-68. IEEE, (2019)Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis., , , and . DATE, page 521-526. IEEE, (2012)A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm., , , and . CICC, page 1-4. IEEE, (2015)FPGA-Based Solid-State Drive Prototyping Platform., , , and . FCCM, page 101-104. IEEE Computer Society, (2011)Low-overhead, digital offset compensated, SRAM sense amplifiers., , , and . CICC, page 705-708. IEEE, (2009)