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PPAC scaling enablement for 5nm mobile SoC technology.

M. Badaroglu, J. Xu, J. Zhu, D. Yang, J. Bao, S. Song, P. Feng, R. Ritzenthaler, H. Mertens, G. Eneman, N. Horiguchi, J. Smith, S. Datta, D. Kohen, P. Chan, K. Chen, and P. Chidambaram. ESSDERC, page 240-243. IEEE, (2017)

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Mustafa Ahmed Mustafa Mustafa University of Stuttgart

Mustafa Kemal Ak University of Stuttgart

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Scalable Gate-Level Models for Power and Timing Analysis.M. Badaroglu, G. der Plas, P. Wambacq, S. Donnay, G. Gielen, and H. Man. ISCAS, page 2938-2941. IEEE, (2007)SWAN: high-level simulation methodology for digital substrate noise generation.M. Badaroglu, G. der Plas, P. Wambacq, S. Donnay, G. Gielen, and H. Man. IEEE Trans. VLSI Syst., 14 (1): 23-33 (2006)High-level simulation of substrate noise generation from large digital circuits with multiple supplies.M. Badaroglu, M. van Heijningen, V. Gravot, S. Donnay, H. Man, G. Gielen, M. Engels, and I. Bolsens. DATE, page 326-330. IEEE Computer Society, (2001)BANDIT: embedding analog-to-digital converters on digital telecom ASICs.S. Donnay, M. van Heijningen, M. Badaroglu, W. Diels, M. Engels, I. Bolsens, Y. Zinzius, G. Gielen, W. Sansen, T. Fondén and 1 other author(s). ICECS, page 1377-1380. IEEE, (1999)Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation.J. Ryckaert, C. Desset, A. Fort, M. Badaroglu, V. Heyn, P. Wambacq, G. der Plas, S. Donnay, B. van Poucke, and B. Gyselinckx. IEEE Trans. on Circuits and Systems, 52-I (12): 2515-2525 (2005)Optimized Signal Acquisition for Low-Complexity and Low-Power IR-UWB Transceivers.C. Desset, M. Badaroglu, J. Ryckaert, and B. van Poucke. VTC Spring, page 3135-3139. IEEE, (2007)Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding.M. Badaroglu, K. Tiri, G. der Plas, P. Wambacq, I. Verbauwhede, S. Donnay, G. Gielen, and H. Man. IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (6): 1146-1154 (2006)High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects.G. der Plas, M. Badaroglu, G. Vandersteen, P. Dobrovolný, P. Wambacq, S. Donnay, G. Gielen, and H. Man. DAC, page 854-859. ACM, (2004)Investigation of electrically gate-all-around hexagonal nanowire FET (HexFET) architecture for 5 nm node logic and SRAM applications.J. Smith, K. Ni, R. Ghosh, J. Xu, M. Badaroglu, P. Chidambaram, and S. Datta. ESSDERC, page 188-191. IEEE, (2017)Interconnect-aware device targeting from PPA perspective.M. Badaroglu, and J. Xu. ICCAD, page 26. ACM, (2016)

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Disambiguation of "Badaroglu, Mustafa"

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PPAC scaling enablement for 5nm mobile SoC technology.

Please choose a person to relate this publication to

Mustafa Ahmed Mustafa Mustafa University of Stuttgart

Mustafa Kemal Ak University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Badaroglu, Mustafa"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML PPAC scaling enablement for 5nm mobile SoC technology.

Please choose a person to relate this publication to

Mustafa Ahmed Mustafa Mustafa University of Stuttgart

Mustafa Kemal Ak University of Stuttgart

Other publications of authors with the same name

Disambiguation

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Chicago
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PPAC scaling enablement for 5nm mobile SoC technology.