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Instruction encoding synthesis for architecture exploration using hierarchical processor models.

, , , , , , and . DAC, page 262-267. ACM, (2003)

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Automatic ADL-based operand isolation for embedded processors., , , , , , , , and . DATE, page 600-605. European Design and Automation Association, Leuven, Belgium, (2006)A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA., , , , , and . ICCAD, page 625-630. IEEE Computer Society, (2001)Processor/Memory Co-Exploration on Multiple Abstraction Levels., , , , , and . DATE, page 10966-10973. IEEE Computer Society, (2003)Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation., , , and . ICCD, page 193-199. IEEE Computer Society, (2005)RTL Processor Synthesis for Architecture Exploration and Implementation., , , , , , , and . DATE, page 156-160. IEEE Computer Society, (2004)A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language., , , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 20 (11): 1338-1354 (2001)Optimization Techniques for ADL-Driven RTL Processor Synthesis., , , , , , and . IEEE International Workshop on Rapid System Prototyping, page 165-171. IEEE Computer Society, (2005)A framework for automated and optimized ASIP implementation supporting multiple hardware description languages., , , , , , and . ASP-DAC, page 280-285. ACM Press, (2005)Optimized ASIP synthesis from architecture description language models., , and . Kluwer, (2007)Architecture Implementation Using the Machine Description Language LISA., , , , and . VLSI Design, page 239-244. IEEE Computer Society, (2002)