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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V.

C. Celio, P. Dabbelt, D. Patterson, and K. Asanovic. CoRR, (2016)

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Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics.C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt and 4 other author(s). IEEE Micro, 29 (4): 8-21 (2009)Real-time Musical Applications on an Experimental Operating System for Multi-Core Processors.J. Colmenares, I. Saxton, E. Battenberg, R. Avizienis, N. Peters, K. Asanovic, J. Kubiatowicz, and D. Wessel. ICMC, Michigan Publishing, (2011)A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.B. Zimmer, Y. Lee, A. Puggelli, J. Kwak, R. Jevtic, B. Keller, S. Bailey, M. Blagojevic, P. Chiu, H. Le and 9 other author(s). VLSIC, page 316-. IEEE, (2015)Accelerating architectural exploration using canonical instruction segments.R. Liu, and K. Asanovic. ISPASS, page 13-24. IEEE Computer Society, (2006)Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks.J. Lee, M. Ng, and K. Asanovic. ISCA, page 89-100. IEEE Computer Society, (2008)The Vector-Thread Architecture.R. Krashinsky, C. Batten, M. Hampton, S. Gerding, B. Pharris, J. Casper, and K. Asanovic. ISCA, page 52-63. IEEE Computer Society, (2004)Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM.B. Zimmer, O. Thomas, S. Toh, T. Vincent, K. Asanovic, and B. Nikolic. ESSDERC, page 98-101. IEEE, (2014)Transactors for parallel hardware and software co-design.K. Asanovic. HLDVT, page 140-142. IEEE Computer Society, (2007)Using PHiPAC to speed error back-propagation learning.J. Bilmes, K. Asanovic, C. Chin, and J. Demmel. ICASSP, page 4153-4156. IEEE Computer Society, (1997)Open-Source EDA Tools and IP, A View from the Trenches.E. Alon, K. Asanovic, J. Bachrach, and B. Nikolic. DAC, page 79. ACM, (2019)

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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V.

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PUMA

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V.

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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V.