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Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses., , , and . DATE, page 628-633. IEEE Computer Society, (2002)On-Chip Inductance Models: 3D or Not 3D?, , and . DATE, page 1112. IEEE Computer Society, (2002)Equipotential shells for efficient inductance extraction., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 20 (1): 70-79 (2001)Electromagnetic parasitic extraction via a multipole method with hierarchical refinement., and . ICCAD, page 437-444. IEEE Computer Society, (1999)Efficient inductance extraction via windowing., and . DATE, page 430-436. IEEE Computer Society, (2001)Parasitics extraction with multipole refinement., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 23 (2): 288-292 (2004)Error bounds for capacitance extraction via window techniques., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 18 (3): 311-321 (1999)On-chip induction modeling: basics and advanced methods., and . IEEE Trans. VLSI Syst., 10 (6): 712-729 (2002)Inductance 101: Modeling and Extraction., and . DAC, page 323-328. ACM, (2001)Modeling Magnetic Coupling for On-Chip Interconnect., and . DAC, page 335-340. ACM, (2001)