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Improving last level shared cache performance through mobile insertion policies (MIP).

P. Fidalgo, P. Prieto, V. Puente, and J. Gregorio. Parallel Computing, (2015)

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Valentin Leipe University of Stuttgart

Valentin Kamm University of Stuttgart

Valentin Wagner University of Stuttgart

Valentin Bayer University of Stuttgart

Valentin Honold University of Stuttgart

Other publications of authors with the same name

Immucube: Scalable Fault-Tolerant Routing for k-ary n-cube Networks.V. Puente, and J. Gregorio. IEEE Trans. Parallel Distrib. Syst., 18 (6): 776-788 (2007)MRR: Enabling fully adaptive multicast routing for CMP interconnection networks.P. Fidalgo, V. Puente, and J. Gregorio. HPCA, page 355-366. IEEE Computer Society, (2009)Immunet: Dependable Routing for Interconnection Networks with Arbitrary Topology.V. Puente, J. Gregorio, F. Vallejo, and R. Beivide. IEEE Trans. Computers, 57 (12): 1676-1689 (2008)Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism.V. Puente, J. Gregorio, F. Vallejo, and R. Beivide. ISCA, page 198-211. IEEE Computer Society, (2004)Improving last level shared cache performance through mobile insertion policies (MIP).P. Fidalgo, P. Prieto, V. Puente, and J. Gregorio. Parallel Computing, (2015)SICOSYS: An Integrated Framework for studying Interconnection Network Performance in Multiprocessor Systems.V. Puente, J. Gregorio, and R. Beivide. PDP, page 15-22. IEEE Computer Society, (2002)Improving parallel system performance by changing the arrangement of the network links.V. Puente, C. Izu, J. Gregorio, R. Beivide, J. Prellezo, and F. Vallejo. ICS, page 44-53. ACM, (2000)A first glance at Kilo-instruction based multiprocessors.M. Galluzzi, V. Puente, A. Cristal, R. Beivide, J. Gregorio, and M. Valero. Conf. Computing Frontiers, page 212-221. ACM, (2004)CLASSIC: A cortex-inspired hardware accelerator.V. Puente, and J. Gregorio. J. Parallel Distrib. Comput., (2019)Adaptive Bubble Router: A Design to Improve Performance in Torus Networks.V. Puente, R. Beivide, J. Gregorio, J. Prellezo, J. Duato, and C. Izu. ICPP, page 58-67. IEEE Computer Society, (1999)

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Disambiguation of "Puente, Valentin"

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Improving last level shared cache performance through mobile insertion policies (MIP).

Please choose a person to relate this publication to

Valentin Leipe University of Stuttgart

Valentin Kamm University of Stuttgart

Valentin Wagner University of Stuttgart

Valentin Bayer University of Stuttgart

Valentin Honold University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Puente, Valentin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Improving last level shared cache performance through mobile insertion policies (MIP).

Please choose a person to relate this publication to

Valentin Leipe University of Stuttgart

Valentin Kamm University of Stuttgart

Valentin Wagner University of Stuttgart

Valentin Bayer University of Stuttgart

Valentin Honold University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

Improving last level shared cache performance through mobile insertion policies (MIP).