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RF potential of a 0.18-/spl mu/m CMOS logic device technology, , , , , , , and . IEEE Transactions on Electron Devices, 47 (4): 864-870 (April 2000)Design Considerations for BEOL MIM Capacitor Modeling in RF CMOS Processes., , , and . VLSI Design, page 188-193. IEEE Computer Society, (2010)RF potential of a 0.18-/spl mu/m CMOS logic technology, , , , , , , , and . International Electron Devices Meeting 1999 : Technical Digest, page 853-856. Piscataway, New Jersey, IEEE, (1999)RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications., , , , , , , , , and . VLSI Design, page 194-199. IEEE Computer Society, (2010)Resonant clock mega-mesh for the IBM z13TM., , , , , , , , , and 2 other author(s). VLSIC, page 322-. IEEE, (2015)Foundation of rf CMOS and SiGe BiCMOS technologies., , , , , , , , , and 12 other author(s). IBM Journal of Research and Development, 47 (2-3): 101-138 (2003)Design automation methodology and rf/analog modeling for rf CMOS and SiGe BiCMOS technologies., , , , , , , , , and 8 other author(s). IBM Journal of Research and Development, 47 (2-3): 139-176 (2003)On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices., , , , , , , , , and 6 other author(s). DAC, page 724-727. ACM, (2003)