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NoC-Based Multiprocessor Architecture for Mixed-Time-Criticality Applications.

, , , , , , , , , and 6 other author(s). Handbook of Hardware/Software Codesign, Springer, (2017)

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Conservative open-page policy for mixed time-criticality memory controllers., , and . DATE, page 525-530. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs., , , , , , , and . DATE, page 495-500. ACM, (2015)Memory-map selection for firm real-time SDRAM controllers., , , and . DATE, page 828-831. IEEE, (2012)NoC-Based Multiprocessor Architecture for Mixed-Time-Criticality Applications., , , , , , , , , and 6 other author(s). Handbook of Hardware/Software Codesign, Springer, (2017)Exploiting expendable process-margins in DRAMs for run-time performance optimization., , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)T-CREST: Time-predictable multi-core architecture for embedded systems., , , , , , , , , and 13 other author(s). Journal of Systems Architecture - Embedded Systems Design, 61 (9): 449-471 (2015)The CompSOC design flow for virtual execution platforms., , , , , and . FPGAworld, page 7:1-7:6. ACM, (2013)A reconfigurable real-time SDRAM controller for mixed time-criticality systems., , , and . CODES+ISSS, page 2:1-2:10. IEEE, (2013)Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling., , , and . IEEE Trans. Computers, 65 (6): 1882-1895 (2016)Virtual execution platforms for mixed-time-criticality systems: the CompSOC architecture and design flow., , , , , , , , , and 2 other author(s). SIGBED Review, 10 (3): 23-34 (2013)