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Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors.

P. Raghavan, A. Lambrechts, M. Jayapala, F. Catthoor, and D. Verkest. DATE, page 339-344. European Design and Automation Association, Leuven, Belgium, (2006)

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Dimensioning for power and performance under 10nm: The limits of FinFETs scaling.M. Bardon, P. Schuddinck, P. Raghavan, D. Jang, D. Yakimets, A. Mercha, D. Verkest, and A. Thean. ICICDT, page 1-4. IEEE, (2015)Modeling FinFET metal gate stack resistance for 14nm node and beyond.K. Miyaguchi, B. Parvais, L. Ragnarsson, P. Wambacq, P. Raghavan, A. Mercha, A. Mocuta, D. Verkest, and A. Thean. ICICDT, page 1-4. IEEE, (2015)A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAMs.B. Zeinali, J. Madsen, P. Raghavan, and F. Moradi. IEEE Trans. Emerging Topics Comput., 7 (2): 294-300 (2019)Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs.R. Patel, K. Xu, E. Friedman, and P. Raghavan. ACM Great Lakes Symposium on VLSI, page 233-238. ACM, (2016)Partitioning and Assignment Exploration for Multiple Modes of IEEE 802.11n Modem on Heterogeneous MPSoC Platforms.P. Agrawal, K. Sugand, M. Palkovic, P. Raghavan, L. der Perre, and F. Catthoor. DSD, page 608-615. IEEE Computer Society, (2012)Coarse-Grained Reconfigurable Array Architectures.B. Sutter, P. Raghavan, and A. Lambrechts. Handbook of Signal Processing Systems, Springer, (2013)Bias Temperature Instability analysis of FinFET based SRAM cells.S. Khan, I. Agbo, S. Hamdioui, H. Kukner, B. Kaczer, P. Raghavan, and F. Catthoor. DATE, page 1-6. European Design and Automation Association, (2014)A multi-threaded coarse-grained array processor for wireless baseband.T. Aa, M. Palkovic, M. Hartmann, P. Raghavan, A. Dejonghe, and L. der Perre. SASP, page 102-107. IEEE Computer Society, (2011)Resolving the memory bottleneck for single supply near-threshold computing.T. Gemmeke, M. Sabry, J. Stuijt, P. Raghavan, F. Catthoor, and D. Atienza. DATE, page 1-6. European Design and Automation Association, (2014)Bias temperature instability analysis in SRAM decoder.S. Khan, S. Hamdioui, H. Kukner, P. Raghavan, and F. Catthoor. ETS, page 1. IEEE Computer Society, (2013)

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Disambiguation of "Raghavan, Praveen"

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Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors.

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Disambiguation of "Raghavan, Praveen"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors.

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Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors.