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VLSI Architecture of Video Post-Processing System for MPEG/H.26X.

, , , , and . NCM, page 1520-1525. IEEE Computer Society, (2009)

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Design and performance evaluation of a 2D-mesh Network on Chip prototype using FPGA., , , , , and . APCCAS, page 1264-1267. IEEE, (2008)Efficient Softmax Hardware Architecture for Deep Neural Networks., , , , , and . ACM Great Lakes Symposium on VLSI, page 75-80. ACM, (2019)VLSI Architecture of Video Post-Processing System for MPEG/H.26X., , , , and . NCM, page 1520-1525. IEEE Computer Society, (2009)Application-level pipelining on Hierarchical NoC., , , , , , , and . ISCAS, page 3873-3876. IEEE, (2010)Scalability Study on Mesh Based Network on Chip., , , , , and . PACIIA (2), page 681-685. IEEE Computer Society, (2008)978-0-7695-3490-9.Performance analysis for matrix-multiplication based on an heterogeneous multi-core SoC., , , and . ASICON, page 1-4. IEEE, (2015)SSS: Self-aware System-on-chip Using a Static-dynamic Hybrid Method., , , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 15 (3): 28:1-28:26 (2019)A technique of automatic monitor generation based on FSM., , , and . APCCAS, page 1775-1778. IEEE, (2008)Meshim: A high-level performance simulation platform for three-dimensional network-on-chip., , and . ASICON, page 349-352. IEEE, (2011)On the Accuracy of Stochastic Delay Bound for Network on Chip., , , , , and . NOCS, page 14:1-14:8. ACM, (2017)