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Disambiguation of "Kodi, Avinash Karanth"

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Energy-efficient adaptive wireless NoCs architecture.

, , , , , and . NOCS, page 1-8. IEEE, (2013)

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Other publications of authors with the same name

Co-design of channel buffers and crossbar organizations in NoCs architectures., , , , and . ICCAD, page 219-226. IEEE Computer Society, (2011)Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures., , , and . ASP-DAC, page 1-6. IEEE, (2009)Packet security with path sensitization for NoCs., and . DATE, page 1136-1139. IEEE, (2016)GARUDA: Designing Energy-Efficient Hardware Monitors From High-Level Policies for Secure Information Flow., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 37 (11): 2509-2518 (2018)Dynamic Power Reduction Techniques in On-Chip Photonic Interconnects., , and . ACM Great Lakes Symposium on VLSI, page 249-252. ACM, (2015)Secure Model Checkers for Network-on-Chip (NoC) Architectures., , and . ACM Great Lakes Symposium on VLSI, page 45-50. ACM, (2016)Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture., , and . ANCS, page 47-56. ACM, (2007)SHARP: Shared Heterogeneous Architecture with Reconfigurable Photonic Network-on-Chip., and . ACM J. Emerg. Technol. Comput. Syst., 14 (2): 25:1-25:22 (2018)Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures., , , and . IEEE Trans. Computers, 64 (12): 3555-3568 (2015)Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors., and . IEEE Micro, 25 (1): 41-49 (2005)