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Disambiguation of "Koneru, Abhishek"

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Accurate Analysis and Prediction of Enterprise Service-Level Performance.

, , , , and . ACM Trans. Design Autom. Electr. Syst., 20 (4): 52:1-52:23 (2015)

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Abhishek Kaushik University of Stuttgart

Abhishek Himmatbhai Borad University of Stuttgart

 

Other publications of authors with the same name

Power-Supply Noise Analysis for Monolithic 3D ICs Using Electrical and Thermal Co-Simulation., , and . ICECS, page 217-220. IEEE, (2018)Re-using BIST for circuit aging monitoring., , , , , and . ETS, page 1-2. IEEE, (2015)Test and Design-for-Testability Solutions for Monolithic 3D Integrated Circuits., and . ACM Great Lakes Symposium on VLSI, page 457-462. ACM, (2019)Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICs., , and . VTS, page 1-6. IEEE, (2019)Analysis of electrostatic coupling in monolithic 3D integrated circuits and its impact on delay testing., and . ETS, page 1-6. IEEE, (2016)Fine-Grained Aging Prediction Based on the Monitoring of Run-Time Stress Using DfT Infrastructure., , , and . ICCAD, page 51-58. IEEE, (2015)Online soft-error vulnerability estimation for memory arrays., , , , and . VTS, page 1-6. IEEE Computer Society, (2016)Accurate Analysis and Prediction of Enterprise Service-Level Performance., , , , and . ACM Trans. Design Autom. Electr. Syst., 20 (4): 52:1-52:23 (2015)Self-awareness and self-learning for resiliency in real-time systems., , , , , and . IOLTS, page 128-131. IEEE, (2015)Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits., , and . JETC, 13 (4): 54:1-54:23 (2017)