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Designing asynchronous circuits from behavioural specifications with internal conflicts.

, , , and . ASYNC, page 106-115. IEEE, (1994)

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Automatic microarchitectural pipelining., , , and . DATE, page 961-964. IEEE, (2010)Optimizing CMOS Circuits for Low Power Using Transistor Reordering., and . ED&TC, page 219-223. IEEE Computer Society, (1996)Process Mining Meets Abstract Interpretation., and . ECML/PKDD (1), volume 6321 of Lecture Notes in Computer Science, page 184-199. Springer, (2010)Elastic systems., , and . MEMOCODE, page 149-158. IEEE Computer Society, (2010)SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits., , , , and . IEEE Trans. on Circuits and Systems, 62-I (9): 2238-2247 (2015)RTL-Aware Dataflow-Driven Macro Placement., , , , and . DATE, page 186-191. IEEE, (2019)Petri Net Analysis Using Boolean Manipulation., , , and . Application and Theory of Petri Nets, volume 815 of Lecture Notes in Computer Science, page 416-435. Springer, (1994)State Encoding of Asynchronous Controllers Using Pseudo-Boolean Optimization., and . ASYNC, page 9-16. IEEE Computer Society, (2018)Verification of timed circuits with symbolic delays., and . ASP-DAC, page 628-633. IEEE Computer Society, (2004)Integrating formal verification in an online judge for e-Learning logic circuit design., , , and . SIGCSE, page 451-456. ACM, (2012)