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Disambiguation of "Pétrot, Frédéric"

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A High Performance Modular Embedded ROM Architecture.

, , and . ISCAS, page 1057-1060. IEEE, (1995)

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Frederic Graeb University of Stuttgart

 

Other publications of authors with the same name

Evaluation of the implementation cost of cache coherence protocols using omniscient actions., and . Design Autom. for Emb. Sys., 14 (1): 21-42 (2010)Native Simulation of MPSoC Using Hardware-Assisted Virtualization., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (7): 1074-1087 (2012)Intégration sur plate-forme matérielle/logicielle de spécifications 'C' parallèles., , , and . Annales des Télécommunications, 59 (7-8): 807-837 (2004)A system-level overview and comparison of three High-Speed Serial Links: USB 3.0, PCI Express 2.0 and LLI 1.0., , , , and . DDECS, page 147-152. IEEE Computer Society, (2013)Service Based Component Design Approach for Flexible Hardware/Software Interface Modeling., , , , , and . IEEE International Workshop on Rapid System Prototyping, page 156-162. IEEE Computer Society, (2006)A System Framework for the Design of Embedded Software Targeting Heterogeneous Multi-core SoCs., and . ASAP, page 153-160. IEEE Computer Society, (2009)Facing ADAS validation complexity with usage oriented testing., , , , , , , , and . CoRR, (2016)Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces., , and . DAC, page 366-375. ACM, (2012)8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links., , , , , , , , , and 4 other author(s). ISSCC, page 146-147. IEEE, (2016)Spidergon STNoC design flow., , , , and . NOCS, page 267-268. ACM/IEEE Computer Society, (2011)