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Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period., , and . IWSOC, page 454-458. IEEE Computer Society, (2005)Optimal design of synchronous circuits using software pipelining techniques., , , and . ACM Trans. Design Autom. Electr. Syst., 6 (4): 516-532 (2001)Implementation of a cycle by cycle variable speed processor., , and . ISCAS (4), page 3335-3338. IEEE, (2005)SPACE: A Hardware/Software SystemC Modeling Platform Including an RTOS., , , , , and . FDL, page 704-716. ECSI, (2003)Performance characterization of an SCMA decoder., , , and . NEWCAS, page 1-4. IEEE, (2016)A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs., , , and . ISCAS, page 633-636. IEEE, (2007)A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs., , and . ISCAS, IEEE, (2006)ESys.Net: a new solution for embedded systems modeling and simulation., , , , , , and . LCTES, page 107-114. ACM, (2004)Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS)., , and . ISCAS, page 1312-1315. IEEE, (2010)Optimal design of synchronous circuits using software pipelining techniques., , , and . ICCD, page 62-67. (1998)