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Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction.

, , , , and . SIGARCH Computer Architecture News, 29 (5): 9-12 (2001)

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Dynamic Tolerance Region Computing for Multimedia., , and . IEEE Trans. Computers, 61 (5): 650-665 (2012)A case for merging the ILP and DLP paradigms., , and . PDP, page 217-224. IEEE Computer Society, (1998)Effective usage of vector registers in decoupled vector architectures., , and . PDP, page 495-501. IEEE Computer Society, (1998)FAME: FAirly MEasuring Multithreaded Architectures., , , , , and . PACT, page 305-316. IEEE Computer Society, (2007)Stencil codes on a vector length agnostic architecture., , , , , , , and . PACT, page 13:1-13:12. ACM, (2018)Runahead Threads: Reducing Resource Contention in SMT Processors., , , and . PACT, page 423. IEEE Computer Society, (2007)Runtime-Guided Management of Scratchpad Memories in Multicore Architectures., , , , , , , and . PACT, page 379-391. IEEE Computer Society, (2015)Efficient runahead threads., , , , and . PACT, page 443-452. ACM, (2010)Power and thermal characterization of POWER6 system., , , , , , , , , and . PACT, page 7-18. ACM, (2010)Initial Evaluation of Multimedia Extensions on VLIW Architectures., and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 403-412. Springer, (2004)