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Certified Timing Verification and the Transition Delay of a Logic Circuit.

S. Devadas, K. Keutzer, S. Malik, and A. Wang. DAC, page 549-555. (1992)

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Offline count-limited certificates.L. Sarmenta, M. van Dijk, J. Rhodes, and S. Devadas. SAC, page 2145-2152. ACM, (2008)Efficient Algorithms for Probing the RNA Mutation Landscape.J. Waldispühl, S. Devadas, B. Berger, and P. Clote. PLoS Computational Biology, (2008)DynaFlow: An Efficient Website Fingerprinting Defense Based on Dynamically-Adjusting Flows.D. Lu, S. Bhat, A. Kwon, and S. Devadas. WPES@CCS, page 109-113. ACM, (2018)Secure Hardware and Cryptography: Contrasts, Synergies and Challenges.S. Devadas. ASHES@CCS, page 1. ACM, (2017)Sanctorum: A lightweight security monitor for secure enclaves.I. Lebedev, K. Hogan, J. Drean, D. Kohlbrenner, D. Lee, K. Asanovic, D. Song, and S. Devadas. DATE, page 1142-1147. IEEE, (2019)On Iterative Collision Search for LPN and Subset Sum.S. Devadas, L. Ren, and H. Xiao. TCC (2), volume 10678 of Lecture Notes in Computer Science, page 729-746. Springer, (2017)Toward a Coherent Multicore Memory Model.S. Devadas. IEEE Computer, 46 (10): 30-31 (2013)Rate Guarantees and Overload Protection in Input-Queued Switches.H. Balakrishnan, S. Devadas, D. Ehlert, and Arvind. INFOCOM, IEEE, (2004)Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems.M. Kinsy, O. Khan, I. Celanovic, D. Majstorovic, N. Celanovic, and S. Devadas. RTSS, page 305-316. IEEE Computer Society, (2011)A framework to accelerate sequential programs on homogeneous multicores.C. Fletcher, R. Harding, O. Khan, and S. Devadas. VLSI-SoC, page 344-347. IEEE, (2013)

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Disambiguation of "Devadas, Srinivas"

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Certified Timing Verification and the Transition Delay of a Logic Circuit.

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Disambiguation of "Devadas, Srinivas"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Certified Timing Verification and the Transition Delay of a Logic Circuit.

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Certified Timing Verification and the Transition Delay of a Logic Circuit.