PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Ubar, Raimund"

Author of the publication

copydeleteadd this publication to your clipboard
Timing simulation of digital circuits with binary decision diagrams.

, , and . DATE, page 460-466. IEEE Computer Society, (2001)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Raimund Koop University of Stuttgart

 

Other publications of authors with the same name

Automated design error debug using high-level decision diagrams and mutation operators., , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 37 (4-5): 505-513 (2013)Fast Test Cost Calculation for Hybrid BIST in Digital Systems., , , , and . DSD, page 318-325. IEEE Computer Society, (2001)Hierarchical Identification of Untestable Faults in Sequential Circuits., , , and . DSD, page 668-671. IEEE Computer Society, (2007)Fault Diagnosis in Integrated Circuits with BIST., , , , and . DSD, page 604-610. IEEE Computer Society, (2007)PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams., , , and . J. Electronic Testing, 25 (6): 289-300 (2009)Functional Built-In Self-Test for processor cores in SoC., , , , and . NORCHIP, page 1-4. IEEE, (2012)Complex delay fault reasoning with sequential 7-valued algebra., , and . LATS, page 1-6. IEEE Computer Society, (2015)Fault simulation with parallel exact critical path tracing in multiple core environment., , and . DATE, page 1180-1185. ACM, (2015)Parallel X-fault simulation with critical path tracing technique., , , and . DATE, page 879-884. IEEE, (2010)Layout to Logic Defect Analysis for Hierarchical Test Generation., , , , and . DDECS, page 35-40. IEEE Computer Society, (2007)