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Disambiguation of "Zambreno, Joseph"

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An FPGA Architecture for the Recovery of WPA/WPA2 Keys.

, , , and . Journal of Circuits, Systems, and Computers, 24 (7): 1550105:1-1550105:26 (2015)

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Dr. Joseph Michaels University of Stuttgart

 

Other publications of authors with the same name

A Reconfigurable Architecture for QR Decomposition Using a Hybrid Approach., , and . ISVLSI, page 541-546. IEEE Computer Society, (2014)A hardware pipeline for accelerating ray traversal algorithms on streaming processors., and . SASP, page 22-29. IEEE Computer Society, (2010)Hardware-software architecture for priority queue management in real-time and embedded systems., , , , , and . IJES, 6 (4): 319-334 (2014)Reconfigurable hardware implementation of a modified chaotic filter bank scheme., and . IJES, 4 (3/4): 248-258 (2010)The secure wavelet transform., and . J. Real-Time Image Processing, 7 (2): 131-142 (2012)A chaotic encryption scheme for real-time embedded systems: design and implementation., and . Telecommunication Systems, 52 (2): 551-561 (2013)Phase Aware Warp Scheduling: Mitigating Effects of Phase Behavior in GPGPU Applications., , , and . PACT, page 1-12. IEEE Computer Society, (2015)Providing secure execution environments with a last line of defense against Trojan circuit attacks., , , and . Computers & Security, 28 (7): 660-669 (2009)A project-based embedded systems design course using a reconfigurable SoC platform., , , and . MSE, page 9-12. IEEE Computer Society, (2015)An FPGA Implementation of the Hestenes-Jacobi Algorithm for Singular Value Decomposition., and . IPDPS Workshops, page 220-227. IEEE Computer Society, (2014)