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Signature Buffer: Bridging Performance Gap between Registers and Caches.

, , and . HPCA, page 164-175. IEEE Computer Society, (2004)

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Performance evaluation of Intel® transactional synchronization extensions for high-performance computing., , , and . SC, page 19:1-19:11. ACM, (2013)Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors., , , , , , , , and . ISCA, page 361-372. IEEE Computer Society, (2014)Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and Stores., , , and . ICCD, page 54-61. IEEE Computer Society, (2001)Scalable Load and Store Processing in Latency-Tolerant Processors., , , , and . IEEE Micro, 26 (1): 30-39 (2006)Address-free memory access based on program syntax correlation of loads and stores., , , and . IEEE Trans. VLSI Syst., 11 (3): 314-324 (2003)Revisit the case for direct-mapped chaches: a case for two-way set-associative level-two caches., , and . ISCA, page 437. ACM, (1992)Dynamic addressing memory arrays with physical locality., , , , and . MICRO, page 161-170. ACM/IEEE Computer Society, (2002)A Minimal Dual-Core Speculative Multi-Threading Architecture., , , and . ICCD, page 360-367. IEEE Computer Society, (2004)Improving in-memory database index performance with Intel® Transactional Synchronization Extensions., , , , , , and . HPCA, page 476-487. IEEE Computer Society, (2014)Signature Buffer: Bridging Performance Gap between Registers and Caches., , and . HPCA, page 164-175. IEEE Computer Society, (2004)