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Disambiguation of "Lamphier, Steve"

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An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management.

, , , , , , , and . J. Solid-State Circuits, 44 (1): 155-162 (2009)

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Other publications of authors with the same name

A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management., , , , , and . ISSCC, page 378-379. IEEE, (2008)Design-for-test methods for stand-alone SRAMs at 1 Gb/s/pin and beyond., , , , and . ITC, page 436-443. IEEE Computer Society, (2000)An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management., , , , , , , and . J. Solid-State Circuits, 44 (1): 155-162 (2009)A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements., , , , , , , , , and 2 other author(s). ISSCC, page 254-256. IEEE, (2011)An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage., , , , , and . J. Solid-State Circuits, 42 (4): 813-819 (2007)A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements., , , , , , , , and . J. Solid-State Circuits, 47 (1): 97-106 (2012)A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology., , , , , and . CICC, page 21-24. IEEE, (2007)A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction., , , , , , , , , and 1 other author(s). ISSCC, page 322-323. IEEE, (2013)