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Disambiguation of "Kim, Chris H."

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A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm.

, , , and . A-SSCC, page 273-276. IEEE, (2018)

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H. Binz

Chris Bühler University of Stuttgart

Kim Meliani University of Stuttgart

H. Bungartz

Joel Kimmich University of Stuttgart

 

Other publications of authors with the same name

Tutorial 2: Low Voltage Circuit Design Techniques for Sub-32nm Technologies.. ISQED, page 4. IEEE Computer Society, (2008)Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design., , , , , and . IEEE Micro, 34 (6): 74-85 (2014)A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations., , , and . IEEE Trans. VLSI Syst., 13 (3): 349-357 (2005)Self Calibrating Circuit Design for Variation Tolerant VLSI Systems., , , , and . IOLTS, page 100-105. IEEE Computer Society, (2005)Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling., , , , and . CICC, page 439-442. IEEE, (2005)Dynamic VTH Scaling Scheme for Active Leakage Power Reduction., and . DATE, page 163-167. IEEE Computer Society, (2002)An SRAM Reliability Test Macro for Fully Automated Statistical Measurements of VMIN Degradation., , and . IEEE Trans. on Circuits and Systems, 59-I (3): 584-593 (2012)A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme., , , and . ISSCC, page 330-606. IEEE, (2007)A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches., , , and . J. Solid-State Circuits, 47 (2): 547-559 (2012)A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory., , , , , and . J. Solid-State Circuits, 48 (2): 598-610 (2013)