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Early experiences in developing and managing the neuroscience gateway.

, , , , , , and . Concurrency and Computation: Practice and Experience, 27 (2): 473-488 (2015)

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Special panel session IIB: "System validation and silicon debug - Is standardization possible?"., , , , , , and . VTS, page 1. IEEE Computer Society, (2016)Innovative Design for Test in State-of-the-Art Analog Systems., , , and . VTS, page 1. IEEE, (2019)Early experiences in developing and managing the neuroscience gateway., , , , , , and . Concurrency and Computation: Practice and Experience, 27 (2): 473-488 (2015)Toward a Computational Steering Framework for Large-Scale Composite Structures Based on Continually and Dynamically Injected Sensor Data., , , , and . ICCS, volume 9 of Procedia Computer Science, page 1149-1158. Elsevier, (2012)The Neuroscience Gateway: Enabling Large Scale Modeling and Data Processing in Neuroscience., , , and . PEARC, page 52:1-52:7. ACM, (2018)Multi-processor Performance on the Tera MTA., , , , , , , and . SC, page 4. IEEE Computer Society, (1998)Introducing The Neuroscience Gateway., , , , , , and . IWSG, volume 993 of CEUR Workshop Proceedings, CEUR-WS.org, (2013)XSEDE13 Special Issue Conference Publications., and . Concurrency and Computation: Practice and Experience, 26 (13): 2107-2111 (2014)