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Multi-port multi-terminal analog router based on an evolutionary optimization kernel., , , and . IEEE Congress on Evolutionary Computation, page 2789-2796. IEEE, (2013)Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks., , , , , , , , and . SMACD, page 1-4. IEEE, (2017)Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs., , , , , , , , and . SMACD, page 1-164. IEEE, (2018)Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer., , , , , , and . Integration, (2016)Electromigration-aware analog Router with multilayer multiport terminal structures., , , and . Integration, 47 (4): 532-547 (2014)Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving., , , , , and . IEEE Trans. on Circuits and Systems, 65-II (11): 1599-1603 (2018)Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization., , , , , and . SMACD, page 285-288. IEEE, (2019)On the Exploration of Promising Analog IC Designs via Artificial Neural Networks., , , , , , and . SMACD, page 133-136. IEEE, (2018)Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing., , , , and . DATE, page 1201-1206. IEEE, (2017)Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop., , , , , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 38 (6): 989-1002 (2019)