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A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery.

M. Harwood, N. Warke, R. Simpson, T. Leslie, A. Amerasekera, S. Batty, D. Colman, E. Carr, V. Gopinathan, S. Hubbins, P. Hunt, A. Joy, P. Khandelwal, B. Killips, T. Krause, S. Lytollis, A. Pickering, M. Saxton, D. Sebastio, G. Swanson, A. Szczepanek, T. Ward, J. Williams, R. Williams, and T. Willwerth. ISSCC, page 436-591. IEEE, (2007)

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Concurrent Optimization of Technology and Design for Nano CMOS.A. Amerasekera. VLSI Design, page 27. IEEE Computer Society, (2007)A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-$m$ CMOS for Nonvolatile Processing in Digital Systems.M. Qazi, A. Amerasekera, and A. Chandrakasan. J. Solid-State Circuits, 49 (1): 202-211 (2014)A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities.P. Raha, S. Randall, R. Jennings, B. Helmick, A. Amerasekera, and B. Haroun. ISQED, page 148-153. IEEE Computer Society, (2002)Ultra low power electronics in the next decade.A. Amerasekera. ISLPED, page 237-238. ACM, (2010)A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery.M. Harwood, N. Warke, R. Simpson, T. Leslie, A. Amerasekera, S. Batty, D. Colman, E. Carr, V. Gopinathan, S. Hubbins and 15 other author(s). ISSCC, page 436-591. IEEE, (2007)The Changing Design Landscape.A. Amerasekera. IEEE Design & Test of Computers, 25 (4): 333 (2008)A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems.M. Qazi, A. Amerasekera, and A. Chandrakasan. ISSCC, page 192-193. IEEE, (2013)ES3: High-speed communications on 4 wheels: What's in your next car?N. Dalt, and A. Amerasekera. ISSCC, page 515. IEEE, (2013)Session 10 overview: Advanced wireline techniques and PLLs: Wireline subcommittee.G. den Besten, and A. Amerasekera. ISSCC, page 174-175. IEEE, (2015)Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links.H. Bae, and A. Amerasekera. ISSCC, page 54-55. IEEE, (2016)

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A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery.

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A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery.