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Disambiguation of "Chou, Shu-Hsuan"

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A Novel mechanism for speed characterization during delay test.

, , , , , and . VTS, page 116-121. IEEE Computer Society, (2011)

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Michel Choudalakis University of Stuttgart

 

Other publications of authors with the same name

VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models., , , and . ISQED, page 535-540. IEEE Computer Society, (2009)dIP: A Non-intrusive Debugging IP for Dynamic Data Race Detection in Many-Core., , and . ISPAN, page 86-91. IEEE Computer Society, (2009)NUDA: A Non-Uniform Debugging Architecture and Nonintrusive Race Detection for Many-Core Systems., , , and . IEEE Trans. Computers, 61 (2): 199-212 (2012)Hierarchical circuit-switched NoC for multicore video processing., , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 35 (2): 182-199 (2011)RunAssert: A non-intrusive run-time assertion for parallel programs debugging., , , and . DATE, page 287-290. IEEE, (2010)An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model., , , , and . DAC, page 652-657. IEEE, (2007)Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications., , , , , and . ICME, page 25-28. IEEE Computer Society, (2006)NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core., , , and . DAC, page 148-153. ACM, (2009)A Novel mechanism for speed characterization during delay test., , , , , and . VTS, page 116-121. IEEE Computer Society, (2011)VisoMT: A Collaborative Multithreading Multicore Processor for Multimedia Applications With a Fast Data Switching Mechanism., , , , , , and . IEEE Trans. Circuits Syst. Video Techn., 19 (11): 1633-1645 (2009)