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Disambiguation of "Sinha, Arani"

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A Novel mechanism for speed characterization during delay test.

, , , , , and . VTS, page 116-121. IEEE Computer Society, (2011)

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Sakshi Sinha University of Stuttgart

 

Other publications of authors with the same name

Path selection based on static timing analysis considering input necessary assignments., , and . VTS, page 1-6. IEEE Computer Society, (2013)Silicon Proven Timing Signoff Methodology using Hazard-Free Robust Path Delay Tests., , and . VTS, page 1-6. IEEE, (2019)Simulating the Effects of Process Variations on Capacitive Crosstalk., , and . ICECS, page 604-607. IEEE, (2006)A Novel mechanism for speed characterization during delay test., , , , , and . VTS, page 116-121. IEEE Computer Society, (2011)An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults., , and . Asian Test Symposium, page 174-177. IEEE Computer Society, (2003)Special session 8C: Panel EDA for analog DFT/ATPG - will SoC cost pressures make this a reality?. VTS, page 259. IEEE Computer Society, (2010)A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults., , and . ATS, page 89-96. IEEE Computer Society, (2008)Location of the Largest Empty Rectangle among Arbitrary Obstacles., , and . FSTTCS, volume 880 of Lecture Notes in Computer Science, page 159-170. Springer, (1994)Panel: Analog Characterization and Test: The Long Road to Realization., , and . VTS, page 337. IEEE Computer Society, (2009)The bang for the buck with resiliency: Yield or field?, and . VTS, page 152. IEEE Computer Society, (2011)