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Variable-Bin-Rate CABAC Engine for H.264/AVC High Definition Real-Time Decoding.

, , and . IEEE Trans. VLSI Syst., 17 (3): 417-426 (2009)

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Algorithmic and architectural co-design for integer motion estimation of AVS., , and . IEEE Trans. Consumer Electronics, 52 (3): 1092-1098 (2006)A flexible VLSI architecture of transport processor for an AVS HDTV decoder SoC., , , , and . IEEE Trans. Consumer Electronics, 52 (4): 1427-1432 (2006)An Efficient Zigzag Scanning and Entropy Coding Architecture Design., , , , , , and . PCM, volume 8294 of Lecture Notes in Computer Science, page 350-358. Springer, (2013)A Motion Vector Predictor Architecture for AVS and MPEG-2 HDTV Decoder., , , , and . PCM, volume 4261 of Lecture Notes in Computer Science, page 424-431. Springer, (2006)Structure preserving single image super-resolution., , , , , and . ICIP, page 1409-1413. IEEE, (2016)A high speed and efficient architecture of VLD for AVS HD video decoder., , , and . PCS, page 377-380. IEEE, (2012)A flexible and high-performance hardware video encoder architecture., , , , and . PCS, page 373-376. IEEE, (2012)An Efficient Reference Frame Storage Scheme for H.264 HDTV Decoder., , , and . ICME, page 361-364. IEEE Computer Society, (2006)An adaptive inter CU depth decision algorithm for HEVC., , , , , , and . VCIP, page 1-4. IEEE, (2015)An AVS HDTV video decoder architecture employing efficient HW/SW partitioning., , , and . IEEE Trans. Consumer Electronics, 52 (4): 1447-1453 (2006)