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Architectural Improvement for a Data-Driven VLSI Processing Array., , and . J. Parallel Distrib. Comput., 19 (4): 308-322 (1993)Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation., and . IEEE Trans. Computers, 40 (1): 66-79 (1991)Foreword to the special issues., and . International Journal of Parallel Programming, 25 (4): 243-244 (1997)Architectural Improvements for Data-Driven VLSI Processing Arrays., , and . FPCA, page 243-259. ACM, (1989)Embedding Tree Stuctures in VLlSI Hexagonal Arrays., , and . IEEE Trans. Computers, 33 (1): 104-107 (1984)An Architectural Framework for Supporting Heterogeneous Instruction-Set Architectures., and . IEEE Computer, 26 (6): 39-56 (1993)An Improved Mapping of Data Flow Programs on a VLSI Array of Processors., and . ICPP, page 871-873. Pennsylvania State University Press, (1987)Overview: The Centre for Advanced Studies., , , and . IBM Systems Journal, 36 (4): 474-488 (1997)Using a Hardware Simulation Engine for Custom MOS Structured Designs., , , and . IBM Journal of Research and Development, 28 (5): 564-571 (1984)The Third International Conference on Parallel Computing Technologies (PaCT-95), Saint Petersburg, Russia.. SIGPLAN Notices, 31 (2): 8-9 (1996)