PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Wu, Allen C.-H."

Author of the publication

copydeleteadd this publication to your clipboard
Youn-Long Steve Lin

, , and . Springer, (1992)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hanchuan Wu University of Stuttgart

H. Binz

H. Bungartz

Yongxiang Wu University of Stuttgart

C. Traut

 

Other publications of authors with the same name

The Design and Inplementation of a Cooperative Design-view Environment for Interactive Partitioning Applications., , and . Softw., Pract. Exper., 26 (10): 1141-1160 (1996)High-Level Synthesis -A Tutorial., and . IEICE Transactions, 78-D (3): 209-218 (1995)Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (3): 564-573 (2007)Multiway FPGA partitioning by fully exploiting design hierarchy., and . ACM Trans. Design Autom. Electr. Syst., 5 (1): 34-50 (2000)Decomposition of instruction decoders for low-power designs., , and . ACM Trans. Design Autom. Electr. Syst., 11 (4): 880-889 (2006)A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 18 (4): 475-483 (1999)TRACER-fpga: a router for RAM-based FPGA's., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 14 (3): 371-374 (1995)A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 16 (10): 1188-1195 (1997)A performance and routability-driven router for FPGAs considering path delays., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 16 (2): 179-185 (1997)Layout-Area Models for High-Level Synthesis., , and . ICCAD, page 34-37. IEEE Computer Society, (1991)