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Disambiguation of "Heittmann, Arne"

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Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation.

, , , , and . Image Processing: Algorithms and Systems, volume 5298 of SPIE Proceedings, page 290-296. SPIE, (2004)

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Other publications of authors with the same name

A hybrid CMOS/memristive nanoelectronic circuit for programming synaptic weights., and . ESANN, (2012)Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation., , , , and . Image Processing: Algorithms and Systems, volume 5298 of SPIE Proceedings, page 290-296. SPIE, (2004)3D Chip Stack Technology Using Through-Chip Interconnects., , , , , , , , and . IEEE Design & Test of Computers, 22 (6): 512-518 (2005)Pulse coupled neural networks with adaptive synapses for image segmentation., , , , and . ARCS Workshops, volume P-41 of LNI, page 275-282. GI, (2004)Modeling variability and irreproducibility of nanoelectronic resistive switches for circuit simulation., and . ASP-DAC, page 503-508. IEEE, (2013)Analysis of the area-delay performance of hybrid nanoelectronic memory cores used in field programmable gate arrays., , and . ACM Great Lakes Symposium on VLSI, page 233-238. ACM, (2013)An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights., , , , and . ICANN, volume 2415 of Lecture Notes in Computer Science, page 1293-1298. Springer, (2002)Limits of writing multivalued resistances in passive nanoelectronic crossbars used in neuromorphic circuits., and . ACM Great Lakes Symposium on VLSI, page 227-232. ACM, (2012)Architecture and optimization of associative memories used for the implementation of logic functions based on nanoelectronic 1S1R cells., and . DATE, page 1496-1499. IEEE, (2018)Variability analysis of a hybrid CMOS/RS nanoelectronic calibration circuit., and . ISCAS, page 1656-1659. IEEE, (2014)