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An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS., , , , , , , , , and . J. Solid-State Circuits, 50 (3): 749-762 (2015)Integrated circuits processing chemical information: Prospects and challenges., , , , and . DATE, page 1. European Design and Automation Association, (2014)An MPSoC for energy-efficient database query processing., , , , , , , , , and 15 other author(s). DAC, page 112:1-112:6. ACM, (2016)A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications., , , , , , , , , and 18 other author(s). DAC, page 47:1-47:6. ACM, (2017)Strategies for initial sizing and operating point analysis of analog circuits., , , , , , , and . DATE, page 1672-1674. IEEE, (2011)Concept of Color Correction on Multi-Channel CMOS Sensors., , and . DICTA, page 771-780. CSIRO Publishing, (2003)A novel ADPLL design using successive approximation frequency control., , , , and . Microelectron. J., 40 (11): 1613-1622 (2009)A 14 bit self-calibrating charge redistribution SAR ADC., , , , and . ISCAS, page 1038-1041. IEEE, (2012)A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology., , , , , and . IEEE Trans. VLSI Syst., 21 (3): 566-570 (2013)Highly integrated packet-based AER communication infrastructure with 3Gevent/S throughput., , , , , , and . ICECS, page 950-953. IEEE, (2010)