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Disambiguation of "Lewis, David M."

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Improving FPGA Performance and Area Using an Adaptive Logic Module.

, , , , , , , , , , , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 135-144. Springer, (2004)

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Dr. Marie Davidova University of Stuttgart

M. Nudischer

M. Kratzer

M. Liewald

M. Fittingho

 

Other publications of authors with the same name

An Empirical Evaluation of Similarity Coefficients for Binary Valued Data., and . IJDWM, 7 (2): 44-66 (2011)Hector: A Hierarchically Structured Shared-memory Multiprocessor., , , and . IEEE Computer, 24 (1): 72-79 (1991)A hierarchical compiled code event-driven logic simulator.. IEEE Trans. on CAD of Integrated Circuits and Systems, 10 (6): 726-737 (1991)A multiple-strength multiple-delay compiled-code logic simulator., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 12 (12): 1937-1946 (1993)The Stratix II logic and routing architecture., , , , , , , , , and 13 other author(s). FPGA, page 14-20. ACM, (2005)Using sparse crossbars within LUT., and . FPGA, page 59-68. ACM, (2001)Architectural enhancements in Stratix-IIITM and Stratix-IVTM., , , , , , and . FPGA, page 33-42. ACM, (2009)The StratixTM routing and logic architecture., , , , , , , , , and 4 other author(s). FPGA, page 12-20. ACM, (2003)Procedural Texture Mapping on FPGAs., and . FPGA, page 112-120. ACM, (1999)Analytical Framework for Switch Block Design., and . FPL, volume 2438 of Lecture Notes in Computer Science, page 122-131. Springer, (2002)