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Disambiguation of "Agarwal, Amit"

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A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking.

, , , , , , , , , and . VLSI Circuits, page 32-. IEEE, (2019)

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Nivedita Agarwal

 

Other publications of authors with the same name

Logarithmic Regret Algorithms for Online Convex Optimization., , , and . COLT, volume 4005 of Lecture Notes in Computer Science, page 499-513. Springer, (2006)Leakage Power Analysis and Reduction for Nanoscale Circuits., , , , and . IEEE Micro, 26 (2): 68-80 (2006)Rectilinear workspace partitioning for parallel coverage using multiple unmanned aerial vehicles., , , and . Advanced Robotics, 21 (1): 105-120 (2007)Co- Location Resistant Virtual Machine Placement in Cloud Data Centers., and . ICPADS, page 61-68. IEEE, (2018)Jupiter Rising: A Decade of Clos Topologies and Centralized Control in Google's Datacenter Network., , , , , , , , , and 8 other author(s). SIGCOMM, page 183-197. ACM, (2015)Agent-based Simultaneous Optimization of Congestion and Air Pollution: A Real-World Case Study., and . ANT/SEIT, volume 52 of Procedia Computer Science, page 914-919. Elsevier, (2015)An Elegant and Computationally Efficient Approach for Heterogeneous Traffic Modelling Using Agent Based Simulation., , , and . ANT/SEIT, volume 52 of Procedia Computer Science, page 962-967. Elsevier, (2015)2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors., , , , , , , , and . IEEE J. Solid State Circuits, 47 (11): 2807-2821 (2012)An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 54 (4): 1074-1085 (2019)A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 56 (4): 1082-1092 (2021)