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An efficient hierarchical timing-driven Steiner tree algorithm for global routing.

J. Xu, X. Hong, T. Jing, Y. Cai, and J. Gu. Integration, 35 (2): 69-84 (2003)

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Other publications of authors with the same name

DFM-aware Routing for Yield Enhancement.X. Hong, Y. Cai, H. Yao, and D. Li. APCCAS, page 1091-1094. IEEE, (2006)Fast congestion-aware timing-driven placement for island FPGA.J. Zhao, Q. Zhou, and Y. Cai. DDECS, page 24-27. IEEE Computer Society, (2009)A thermal-driven force-directed floorplanning algorithm for 3D ICs.Y. Huang, Q. Zhou, Y. Cai, and H. Yan. CAD/Graphics, page 497-502. IEEE, (2009)Bridging the Gap between Global Routing and Detailed Routing: A Practical Congestion Model.Z. Qi, Y. Cai, and Q. Zhou. CAD/Graphics, page 74-80. IEEE, (2013)Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.W. Shen, Y. Cai, X. Hong, and J. Hu. ISVLSI, page 383-388. IEEE Computer Society, (2007)Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan.X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C. Cheng, and J. Gu. ICCAD, page 8-12. IEEE Computer Society, (2000)A novel fine-grain track routing approach for routability and crosstalk optimization.Z. Qi, Q. Zhou, Y. Jia, Y. Cai, Z. Li, and H. Yao. ISQED, page 621-626. IEEE, (2011)SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography.Z. Chen, H. Yao, and Y. Cai. ISQED, page 566-571. IEEE, (2013)Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding.X. Wang, Q. Zhou, Y. Cai, and G. Qu. Integration, (2019)Register placement for low power clock network.Y. Lu, C. Sze, X. Hong, Q. Zhou, Y. Cai, L. Huang, and J. Hu. ASP-DAC, page 588-593. ACM Press, (2005)

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An efficient hierarchical timing-driven Steiner tree algorithm for global routing.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An efficient hierarchical timing-driven Steiner tree algorithm for global routing.

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An efficient hierarchical timing-driven Steiner tree algorithm for global routing.