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Digital Window Comparator DfT Scheme for Mixed-Signal ICs.

, , and . J. Electronic Testing, 18 (2): 121-128 (2002)

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Realistic-Faults Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits.. ITC, page 776-785. IEEE Computer Society, (1996)On-Chip Test for Mixed-Signal ASICs using Two-Mode Comparators with Bias-Programmable Reference Voltages., and . J. Electronic Testing, 17 (3-4): 243-253 (2001)Floating body effects model for fault simulation of fully depleted CMOS/SOI circuits., and . Microelectronics Journal, 34 (10): 889-895 (2003)Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits., , and . ED&TC, page 464-468. IEEE Computer Society, (1995)A Design for Testability Study on a High Performance Automatic Gain Control Circuit., , , and . VTS, page 376-385. IEEE Computer Society, (1998)Automatic Repositioning Technique for Digital Cell Based Window Comparators and Implementation within Mixed-Signal DfT Schemes., , and . ISQED, page 431-437. IEEE Computer Society, (2003)Testing of Analogue Circuits via (Standard) Digital Gates., , and . ISQED, page 112-119. IEEE Computer Society, (2002)Test of Digital Transversal Filters., and . ITC, page 842-847. IEEE Computer Society, (1985)Digital Window Comparator DfT Scheme for Mixed-Signal ICs., , and . J. Electronic Testing, 18 (2): 121-128 (2002)Design, qualification and production of integrated sensor interface circuits for high-quality automotive applications., and . Microelectronics Journal, 40 (9): 1350-1357 (2009)