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Disambiguation of "Watanabe, Kazunori"

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A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW.

, , , , , , , and . VLSIC, page 194-195. IEEE, (2012)

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Other publications of authors with the same name

A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS., , , , , , , and . ASP-DAC, page 109-110. IEEE, (2013)0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS., , , , , , , and . CICC, page 1-4. IEEE, (2010)315MHz OOK transceiver with 38-µW receiver and 36-µW transmitter in 40-nm CMOS., , , , , , and . ASP-DAC, page 93-94. IEEE, (2013)A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW., , , , , , , and . VLSIC, page 194-195. IEEE, (2012)Splicing of Single-Mode Optical Fibers and Jointing of Fiber Cables., , , , , and . ICC (3), page 1080-1083. Elsevier, (1984)Design Method of Class-F Power Amplifier With Output Power of -20 dBm and Efficient Dual Supply Voltage Transmitter., , , , and . IEEE Trans. on Circuits and Systems, 61-I (10): 2978-2986 (2014)A 1-V-Input Switched-Capacitor Voltage Converter With Voltage-Reference-Free Pulse-Density Modulation., , , , , , , , and . IEEE Trans. on Circuits and Systems, 59-II (6): 361-365 (2012)2.1 Times increase of drain efficiency by dual supply voltage scheme in 315MHz class-F Power amplifier at output power of -20dBm., , , , and . ESSCIRC, page 345-348. IEEE, (2012)A 0.6 V Input CCM/DCM Operating Digital Buck Converter in 40 nm CMOS., , , , , , , and . J. Solid-State Circuits, 49 (11): 2377-2386 (2014)An all 0.5V, 1Mbps, 315MHz OOK transceiver with 38-µW career-frequency-free intermittent sampling receiver and 52-µW class-F transmitter in 40-nm CMOS., , , , , , and . VLSIC, page 38-39. IEEE, (2012)