%0 Conference Paper %1 conf/vlsic/ZhangCRIOWST12 %A Zhang, Xin %A Chen, Po-Hung %A Ryu, Yoshikatsu %A Ishida, Koichi %A Okuma, Yasuyuki %A Watanabe, Kazunori %A Sakurai, Takayasu %A Takamiya, Makoto %B VLSIC %D 2012 %I IEEE %K dblp %P 194-195 %T A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2012.html#ZhangCRIOWST12 %@ 978-1-4673-0848-9

@inproceedings{conf/vlsic/ZhangCRIOWST12, added-at = {2016-03-16T00:00:00.000+0100}, author = {Zhang, Xin and Chen, Po-Hung and Ryu, Yoshikatsu and Ishida, Koichi and Okuma, Yasuyuki and Watanabe, Kazunori and Sakurai, Takayasu and Takamiya, Makoto}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2c477dd13e61b7bb6525be6c45c2ecf9e/dblp}, booktitle = {VLSIC}, crossref = {conf/vlsic/2012}, ee = {http://dx.doi.org/10.1109/VLSIC.2012.6243856}, interhash = {b15308694efe26f8a17c8eb141e5ac12}, intrahash = {c477dd13e61b7bb6525be6c45c2ecf9e}, isbn = {978-1-4673-0848-9}, keywords = {dblp}, pages = {194-195}, publisher = {IEEE}, timestamp = {2016-03-17T10:33:16.000+0100}, title = {A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2012.html#ZhangCRIOWST12}, year = 2012 }