Author of the publication

Optical computing on silicon-on-insulator-based photonic integrated circuits.

, , , , , and . ASICON, page 472-475. IEEE, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Total power optimization combining placement, sizing and multi-Vt through slack distribution management., , and . ASP-DAC, page 352-357. IEEE, (2008)BOB-router: A new buffering-aware global router with over-the-block routing resources optimization., , and . ASP-DAC, page 513-518. IEEE, (2014)Self-aligned double patterning layout decomposition with complementary e-beam lithography., , and . ASP-DAC, page 143-148. IEEE, (2014)Global Routing., and . Encyclopedia of Algorithms, (2016)Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization., , , , , , , and . IEEE Trans. VLSI Syst., 26 (9): 1613-1626 (2018)A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library., , , and . CICC, page 1-4. IEEE, (2019)Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree construction., , , and . ICCAD, page 137-143. ACM, (2012)A unified non-rectangular device and circuit simulation model for timing and power., , and . ICCAD, page 423-428. ACM, (2006)DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement., , , , , and . DAC, page 117. ACM, (2019)Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization., , , , , and . ACM Great Lakes Symposium on VLSI, page 87-90. ACM, (2015)