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Architectures and modeling of predictable memory controllers for improved system integration.

, and . DATE, page 851-856. IEEE, (2011)

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Improved Power Modeling of DDR SDRAMs., , and . DSD, page 99-108. IEEE Computer Society, (2011)Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield., , and . ISQED, page 41-48. IEEE, (2012)Architectures and modeling of predictable memory controllers for improved system integration., and . DATE, page 851-856. IEEE, (2011)Exploiting expendable process-margins in DRAMs for run-time performance optimization., , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Generalized Extraction of Real-Time Parameters for Homogeneous Synchronous Dataflow Graphs., , and . PDP, page 701-710. IEEE Computer Society, (2015)Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs., , and . ACM Trans. Embedded Comput. Syst., 13 (2s): 61:1-61:24 (2014)T-CREST: Time-predictable multi-core architecture for embedded systems., , , , , , , , , and 13 other author(s). Journal of Systems Architecture - Embedded Systems Design, 61 (9): 449-471 (2015)Dynamic Command Scheduling for Real-Time Memory Controllers., , and . ECRTS, page 3-14. IEEE Computer Society, (2014)Run-time power-down strategies for real-time SDRAM memory controllers., , and . DAC, page 988-993. ACM, (2012)Composable Resource Sharing Based on Latency-Rate Servers., , and . DSD, page 547-555. IEEE Computer Society, (2009)