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Disambiguation of "Chandrasekar, Karthik"

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Improved Power Modeling of DDR SDRAMs.

, , and . DSD, page 99-108. IEEE Computer Society, (2011)

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Karthik Pandaram University of Stuttgart

 

Other publications of authors with the same name

TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration., , , and . RAPIDO, page 5:1-5:6. ACM, (2013)On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system., , , , , , , , , and 8 other author(s). IPDPS, page 1-8. IEEE, (2008)Future generation supercomputers I: a paradigm for node architecture., , , , , , , , , and 1 other author(s). SIGARCH Computer Architecture News, 35 (5): 49-60 (2007)QoS Monitoring and Dynamic Trust Establishment in the Cloud., , , and . GPC, volume 7296 of Lecture Notes in Computer Science, page 289-301. Springer, (2012)Improved Power Modeling of DDR SDRAMs., , and . DSD, page 99-108. IEEE Computer Society, (2011)Exploiting expendable process-margins in DRAMs for run-time performance optimization., , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Design for Testability of Functional Cores in High Performance Node Architectures., , and . DELTA, page 302-307. IEEE Computer Society, (2008)Energy Conservative Mobile Cloud Infrastructure., , , and . GPC, volume 7296 of Lecture Notes in Computer Science, page 152-161. Springer, (2012)Run-time power-down strategies for real-time SDRAM memory controllers., , and . DAC, page 988-993. ACM, (2012)System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs., , , , and . DATE, page 236-241. EDA Consortium San Jose, CA, USA / ACM DL, (2013)