PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Fujishima, Minoru"

Author of the publication

copydeleteadd this publication to your clipboard
Device Modeling Techniques for High-Frequency Circuits Design Using Bond-Based Design at over 100 GHz.

, , , , and . IEICE Transactions, 94-C (4): 589-597 (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Fujishima, Minoru
add a person with the name Fujishima, Minoru
 

Other publications of authors with the same name

98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits., , , , , and . J. Solid-State Circuits, 48 (10): 2273-2284 (2013)In Situ Evaluation Method for On-Chip Inductors Using Oscillator Response., and . CICC, page 369-372. IEEE, (2006)135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS., , , , , and . VLSIC, page 50-51. IEEE, (2012)High-speed and wide-tuning-range LC frequency dividers., , and . ISCAS (4), page 361-364. IEEE, (2004)High-speed processor for quantum-computing emulation and its applications., , , and . ISCAS (4), page 884-887. IEEE, (2003)High-Attenuation Power Line for Wideband Decoupling., , and . IEICE Transactions, 92-C (6): 792-797 (2009)Foreword.. IEICE Transactions, 99-C (4): 430 (2016)A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology., , , , and . IEICE Transactions, 95-C (7): 1154-1162 (2012)9dB NF and +11dBm OIP3 CMOS Single Conversion Front-End for a Satellite Low-Noise Block Down-Converter., , , , and . IEICE Transactions, 97-A (1): 101-108 (2014)A 37-GHz-Input Divide-by-36 Injection-Locked Frequency Divider with 1.6-GHz Lock Range., , , , , and . A-SSCC, page 219-222. IEEE, (2018)