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Disambiguation of "Takano, Kyoya"

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A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology.

, , , , and . IEICE Transactions, 95-C (7): 1154-1162 (2012)

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Other publications of authors with the same name

Tehrahertz CMOS Design for Low-Power and High-Speed Wireless Communication., , , , and . IEICE Transactions, 98-C (12): 1091-1104 (2015)Bias-Voltage-Dependent Subcircuit Model for Millimeter-Wave CMOS Circuit., , , , and . IEICE Transactions, 95-C (6): 1077-1085 (2012)98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits., , , , , and . J. Solid-State Circuits, 48 (10): 2273-2284 (2013)135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS., , , , , and . VLSIC, page 50-51. IEEE, (2012)A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology., , , , and . IEICE Transactions, 95-C (7): 1154-1162 (2012)A 37-GHz-Input Divide-by-36 Injection-Locked Frequency Divider with 1.6-GHz Lock Range., , , , , and . A-SSCC, page 219-222. IEEE, (2018)A 120 GHz/140 GHz Dual-Channel OOK Receiver Using 65 nm CMOS Technology., , , and . IEICE Transactions, 96-A (2): 486-493 (2013)E-Band 65nm CMOS Low-Noise Amplifier Design Using Gain-Boost Technique., , , , , and . IEICE Transactions, 97-C (6): 476-485 (2014)Power-amplifier-inserted Transversal Filter that Recovers Quantization Noise Power by CMOS Rectifier., , and . ICECS, page 653-654. IEEE, (2018)A Scalable Model of Shielded Capacitors Using Mirror Image Effects., , , and . IEICE Transactions, 90-C (12): 2237-2244 (2007)