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Analyzing Reliability of Memory Sub-systems with Double-Chipkill Detect/Correct.

, , , , and . PRDC, page 88-97. IEEE Computer Society, (2013)

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Balancing Performance and Reliability in the Memory Hierarchy., , , and . ISPASS, page 269-279. IEEE Computer Society, (2005)Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults., , , , , and . MICRO, page 293-305. IEEE, (2014)Vulnerability analysis of L2 cache elements to single event upsets., , , and . DATE, page 1276-1281. European Design and Automation Association, Leuven, Belgium, (2006)Reducing Data Cache Susceptibility to Soft Errors., , , and . IEEE Trans. Dependable Sec. Comput., 3 (4): 353-364 (2006)Faults in data prefetchers: Performance degradation and variability., , , , and . VTS, page 1-6. IEEE Computer Society, (2016)Assessing the impact of hard faults in performance components of modern microprocessors., , , and . ICCD, page 207-214. IEEE Computer Society, (2013)Nonblocking DRAM Refresh., , , , and . IEEE Micro, 39 (3): 103-109 (2019)Low-power, low-storage-overhead chipkill correct via multi-line error correction., , , , and . SC, page 24:1-24:12. ACM, (2013)Lessons learned from memory errors observed over the lifetime of Cielo., , , , , and . SC, page 43:1-43:12. IEEE / ACM, (2018)A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches., , , and . IEEE Micro, 34 (3): 80-90 (2014)