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Disambiguation of "Noia, Brandon"

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Test and Design-for-Testability Solutions for 3D Integrated Circuits.

, , , , , and . IPSJ Trans. System LSI Design Methodology, (2014)

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Other publications of authors with the same name

Post-DfT-insertion retiming for delay recovery on inter-die paths in 3D ICs., and . VTS, page 1-6. IEEE Computer Society, (2013)Scan test of die logic in 3D ICs using TSV probing., , , and . ITC, page 1-8. IEEE Computer Society, (2012)Test and Design-for-Testability Solutions for 3D Integrated Circuits., , , , , and . IPSJ Trans. System LSI Design Methodology, (2014)Optimization Methods for Post-Bond Testing of 3D Stacked ICs., , and . J. Electronic Testing, 28 (1): 103-120 (2012)Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (11): 1705-1718 (2011)Optimization methods for post-bond die-internal/external testing in 3D stacked ICs., , and . ITC, page 193-201. IEEE Computer Society, (2010)Pre-bond probing of TSVs in 3D stacked ICs., and . ITC, page 1-10. IEEE Computer Society, (2011)Pre-bond testing of die logic and TSVs in high performance 3D-SICs., and . 3DIC, page 1-5. IEEE, (2011)Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs., and . Springer, (2014)Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs., , and . ICCD, page 70-77. IEEE Computer Society, (2009)