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A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver.

J. Moody, A. Dissanayake, H. Bishop, R. Lu, N. Liu, D. Duvvuri, A. Gao, D. Truesdell, N. Barker, S. Gong, B. Calhoun, and S. Bowers. VLSI Circuits, page 86-. IEEE, (2019)

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Dexing Liu University of Stuttgart

Jan Liu University of Stuttgart

M.Sc. Zhuoran Liu University of Stuttgart

Shuang Liu University of Stuttgart

Yanchao Liu University of Stuttgart

Other publications of authors with the same name

Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process.Z. Yu, Z. Yu, X. Yu, N. Liu, and X. Zeng. IEEE Trans. on Circuits and Systems, 61-II (6): 423-427 (2014)A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors.A. Banerjee, N. Liu, H. Patel, B. Calhoun, J. Poulton, and C. Gray. CICC, page 1-4. IEEE, (2017)A 2.5 ppm/°C 1.05-MHz Relaxation Oscillator With Dynamic Frequency-Error Compensation and Fast Start-Up Time.N. Liu, R. Agarwala, A. Dissanayake, D. Truesdell, S. Kamineni, and B. Calhoun. J. Solid-State Circuits, 54 (7): 1952-1959 (2019)A 1.02 μW Battery-Less, Continuous Sensing and Post-Processing SiP for Wearable Applications.C. Lukas, F. Yahya, J. Breiholz, A. Roy, X. Chen, H. Patel, N. Liu, A. Kosari, S. Li, D. Kamakshi and 3 other author(s). IEEE Trans. Biomed. Circuits and Systems, 13 (2): 271-281 (2019)Novel operation scheme and technological optimization for 1T bulk capacitor-less DRAM.H. Li, W. Zhu, N. Liu, C. Dong, C. Meng, Y. Lin, R. Huang, Q. Zou, and J. Wu. ASICON, page 1-3. IEEE, (2013)A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic.H. Patel, A. Roy, F. Yahya, N. Liu, B. Calhoun, K. Kumeno, M. Yasuda, A. Harada, and T. Ema. ESSCIRC, page 45-48. IEEE, (2016)Design Optimization of Register File Throughput and Energy Using a Virtual Prototyping (ViPro) Tool.N. Liu, and B. Calhoun. ISVLSI, page 535-540. IEEE Computer Society, (2016)Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference.A. Rekhi, B. Zimmer, N. Nedovic, N. Liu, R. Venkatesan, M. Wang, B. Khailany, W. Dally, and C. Gray. DAC, page 81. ACM, (2019)Low-power high-yield SRAM design with VSS adaptive boosting and BL capacitance variation sensing.N. Liu, Y. Jiang, Q. Dong, H. Li, X. Hu, and Y. Lin. ASICON, page 1-4. IEEE, (2013)A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-up Time.N. Liu, R. Agarwala, A. Dissanayake, D. Truesdell, S. Kamineni, X. Chen, D. Wentzloff, and B. Calhoun. ESSCIRC, page 150-153. IEEE, (2018)

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Disambiguation of "Liu, Ningxi"

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A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver.

Please choose a person to relate this publication to

Dexing Liu University of Stuttgart

Jan Liu University of Stuttgart

M.Sc. Zhuoran Liu University of Stuttgart

Shuang Liu University of Stuttgart

Yanchao Liu University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Liu, Ningxi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver.

Please choose a person to relate this publication to

Dexing Liu University of Stuttgart

Jan Liu University of Stuttgart

M.Sc. Zhuoran Liu University of Stuttgart

Shuang Liu University of Stuttgart

Yanchao Liu University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
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MSOffice XML

A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver.