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Constraints on sequence processing speed in biological neuronal networks., , , , and . ICONS, page 16:1-16:9. ACM, (2019)Memristor based computation-in-memory architecture for data-intensive applications., , , , , , , , , and 1 other author(s). DATE, page 1718-1725. ACM, (2015)Phase-Change and Redox-Based Resistive Switching Memories., , and . Proceedings of the IEEE, 103 (8): 1274-1288 (2015)Memristive Device Modeling and Circuit Design Exploration for Computation-in-Memory., , , and . ISCAS, page 1-5. IEEE, (2019)Analysis of the effect of cell parameters on the maximum RRAM array size considering both read and write., , , , and . ESSDERC, page 282-285. IEEE, (2012)The influence of interfacial (sub)oxide layers on the properties of pristine resistive switching devices., , , , , and . NVMTS, page 1-4. IEEE, (2018)Lowering forming voltage and forming-free behavior of Ta2O5 ReRAM devices., , , , , and . ESSDERC, page 164-167. IEEE, (2016)In-Memory Binary Vector-Matrix Multiplication Based on Complementary Resistive Switches., , , and . Adv. Intell. Syst., 2 (10): 2000134 (2020)