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An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions., , and . DDECS, page 158-163. IEEE Computer Society, (2009)Delay Testing Viability of Gate Oxide Short Defects., , , and . J. Comput. Sci. Technol., 20 (2): 195-200 (2005)Algebraic Specification of a 3D-Modeler Based on Hypermaps., and . CVGIP: Graphical Model and Image Processing, 56 (1): 29-60 (1994)A New Methodology For ADC Test Flow Optimization., , , , and . ITC, page 201-209. IEEE Computer Society, (2003)Remote Labs for Industrial IC Testing., , , , and . TLT, 2 (4): 304-311 (2009)A-to-D converters static error detection from dynamic parameter measurement., , , , and . Microelectronics Journal, 34 (10): 945-953 (2003)Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST., , , and . J. Electronic Testing, 17 (3-4): 255-266 (2001)A Low-Cost Adaptive Ramp Generator for Analog BIST Applications., , , , and . VTS, page 266-271. IEEE Computer Society, (2001)On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems., , , and . DATE, page 1120. IEEE Computer Society, (2002)Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits., , and . DATE, page 815-821. IEEE Computer Society, (1998)