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Unified On-Chip Software and Hardware Debug for HLS-Accelerated Programs., and . FPT, page 354-357. IEEE, (2018)Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays., , , and . TRETS, 13 (1): 4:1-4:26 (2020)Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage Devices.. FCCM, page 136-143. IEEE Computer Society, (2017)Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs., and . FPT, page 40-47. IEEE, (2015)Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 36 (1): 83-96 (2017)Quantifying observability for in-system debug of high-level synthesis circuits., and . FPL, page 1-11. IEEE, (2016)Architecture Exploration for HLS-Oriented FPGA Debug Overlays., , and . FPGA, page 209-218. ACM, (2018)An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug., , and . FPL, page 403-410. IEEE Computer Society, (2018)On-chip FPGA Debug Instrumentation for Machine Learning Applications., , , , and . FPGA, page 110-115. ACM, (2019)The VTR project: architecture and CAD for FPGAs from verilog to routing., , , , , , , , and . FPGA, page 77-86. ACM, (2012)