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On-chip FPGA Debug Instrumentation for Machine Learning Applications.

D. Noronha, R. Zhao, J. Goeders, W. Luk, and S. Wilton. FPGA, page 110-115. ACM, (2019)

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Jiachen Zhao University of Stuttgart

Jianyu Zhao University of Stuttgart

Zhibin Zhao University of Stuttgart

Other publications of authors with the same name

Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms.R. Zhao, X. Niu, Y. Wu, W. Luk, and Q. Liu. ARC, volume 10216 of Lecture Notes in Computer Science, page 255-267. (2017)Learning Grouped Convolution for Efficient Domain Adaptation.R. Zhao, and W. Luk. CoRR, (2018)Reconfigurable Hardware Generation for Tensor Flow Models of CNN Algorithms on a Heterogeneous Acceleration Platform.J. Gao, Y. Zhu, M. Qiu, K. Tsoi, X. Niu, W. Luk, R. Zhao, Z. Que, W. Mao, C. Feng and 4 other author(s). SmartCom, volume 11344 of Lecture Notes in Computer Science, page 87-96. Springer, (2018)Hardware Compilation of Deep Neural Networks: An Overview.R. Zhao, S. Liu, H. Ng, E. Wang, J. Davis, X. Niu, X. Wang, H. Shi, G. Constantinides, P. Cheung and 1 other author(s). ASAP, page 1-8. IEEE Computer Society, (2018)Multichannel vectorial holographic display and encryptionR. Zhao, B. Sain, Q. Wei, C. Tang, X. Li, T. Weiss, L. Huang, Y. Wang, and T. Zentgraf. Light : Science & Applications, (2018)Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going.E. Wang, J. Davis, R. Zhao, H. Ng, X. Niu, W. Luk, P. Cheung, and G. Constantinides. ACM Comput. Surv., 52 (2): 40:1-40:39 (2019)Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA.R. Zhao, H. Ng, W. Luk, and X. Niu. FPL, page 147-154. IEEE Computer Society, (2018)A genome-wide cis-regulatory element discovery method based on promoter sequences and gene co-expression networks.Z. Gao, R. Zhao, and J. Ruan. RACS, page 74-75. ACM, (2012)Hardware Acceleration for Machine Learning.R. Zhao, W. Luk, X. Niu, H. Shi, and H. Wang. ISVLSI, page 645-650. IEEE Computer Society, (2017)Optimizing and auto-tuning scale-free sparse matrix-vector multiplication on Intel Xeon Phi.W. Tang, R. Zhao, M. Lu, Y. Liang, H. Huyng, X. Li, and R. Goh. CGO, page 136-145. IEEE Computer Society, (2015)

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Disambiguation of "Zhao, Ruizhe"

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On-chip FPGA Debug Instrumentation for Machine Learning Applications.

Please choose a person to relate this publication to

Jiachen Zhao University of Stuttgart

Jianyu Zhao University of Stuttgart

Zhibin Zhao University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Zhao, Ruizhe"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML On-chip FPGA Debug Instrumentation for Machine Learning Applications.

Please choose a person to relate this publication to

Jiachen Zhao University of Stuttgart

Jianyu Zhao University of Stuttgart

Zhibin Zhao University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

On-chip FPGA Debug Instrumentation for Machine Learning Applications.